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Soumil Hooda
Silicon Engineer at Google
I graduated in 2025 from BITS Pilani, Hyderabad, with a dual degree: a Bachelor of Engineering in Electrical and Electronics, and a Master of Science in Physics.
Over the years, I’ve had the chance to work across a range of research settings that sit at the intersection of machine learning and physical systems.
At the Space Applications Centre (ISRO) and CSIR–CEERI, I explored applied ML in remote sensing, atmospheric modelling, healthcare, and Brain–Computer Interfaces.
Along the way, I was fortunate to learn from mentors including
Prof. Manik Gupta,
Prof. Rajesh Tripathy, and
Dr. Satya Prakash Ojha.
Another major focus of mine has been weather risk management in India—an area I believe is still structurally underserved.
I’ve worked on designing and analyzing financial instruments such as temperature-based derivatives, rainfall–agriculture quanto contracts, and wind/solar energy swaps,
alongside studying securitization strategies for schemes like PMFBY and WBCIS.
This line of work gradually evolved from academic curiosity into a more product-oriented effort.
Please click here if you’d like to read a more personal account of this.
On the industry side, I’ve spent time working close to silicon.
During my internship at Texas Instruments, I worked on developing an assertion-based formal verification IP for a real-time microcontroller platform,
with a focus on reusable, property-driven verification infrastructure.
Alongside this, I independently explored representing finite-state machines as graphs and experimenting with GNN-based approaches to analyze their behavior,
primarily as an exploratory exercise to understand the limits of conventional verification workflows.
I later interned at Google, where I worked on infrastructure for generating and integrating subsystem-level RTL based on architectural configuration.
The work touched the full spectrum of auxiliary logic bring-up—spanning power intent, clock/reset domain crossing, linting, and register collateral—
and gave me a systems-level view of how large SoC blocks are stitched together.
I now work full-time at Google as a Silicon Engineer on a first-party cache-coherent interconnect IP.
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